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| VN920DSP HIGH SIDE DRIVER Table 1. General Features Type VN920DSP RDS(on) 16 m Figure 1. Package Iout 25 A VCC 36 V CMOS COMPATIBLE INPUT ON STATE OPEN LOAD DETECTION s OFF STATE OPEN LOAD DETECTION s SHORTED LOAD PROTECTION s UNDERVOLTAGE AND OVERVOLTAGE SHUTDOWN s PROTECTION AGAINST LOSS OF GROUND s VERY LOW STAND-BY CURRENT s s s 10 1 PowerSO-10 REVERSE BATTERY PROTECTION (*) DESCRIPTION The VN920DSP is a monolithic device made by using STMicroelectronics VIPower M0-3 Technology, intended for driving any kind of load with one side connected to ground. Active V CC pin voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table). Active current limitation combined with thermal shutdown and automatic restart protect the device against overload. The device detects open load condition both is on and off state. Output shorted to VCC is detected in the off state. Device automatically turns off in case of ground pin disconnection. Table 2. Order Codes Package PowerSO-10TM Note: (*) See application schematic at page 9 Tube VN920DSP Tape and Reel VN920DSP13TR Rev. 2 October 2004 1/19 VN920DSP Figure 2. Block Diagram VCC VCC CLAMP OVERVOLTAGE DETECTION UNDERVOLTAGE DETECTION GND Power CLAMP INPUT LOGIC DRIVER OUTPUT CURRENT LIMITER STATUS ON STATE OPENLOAD DETECTION OVERTEMPERATURE DETECTION OFF STATE OPENLOAD AND OUTPUT SHORTED TO VCC DETECTION Table 3. Absolute Maximum Ratings Symbol VCC - VCC - IGND IOUT - IOUT IIN ISTAT Parameter DC Supply Voltage Reverse DC Supply Voltage DC Reverse Ground Pin Current DC Output Current Reverse DC Output Current DC Input Current DC Status Current Electrostatic Discharge (Human Body Model: R=1.5K; C=100pF) - INPUT VESD - CURRENT SENSE - OUTPUT - VCC Maximum Switching Energy (L=0.25mH; RL=0; Vbat=13.5V; Tjstart=150C; IL=45A) Power Dissipation TC=25C Junction Operating Temperature Case Operating Temperature Storage Temperature Value 41 - 0.3 - 200 Internally Limited - 25 +/- 10 +/- 10 4000 4000 5000 5000 362 96.1 Internally Limited - 40 to 150 - 55 to 150 Unit V V mA A A mA mA V V V V mJ W C C C EMAX Ptot Tj Tc Tstg 2/19 VN920DSP Figure 3. Configuration Diagram (Top View) & Suggested Connections for Unused and N.C. Pins GROUND INPUT STATUS N.C. N.C. 6 7 8 9 10 11 5 4 3 2 1 OUTPUT OUTPUT N.C. OUTPUT OUTPUT VCC Connection / Pin Floating To Ground Status X N.C. X X Output X Input X Through 10K resistor Figure 4. Current and Voltage Conventions IS VCC VF VCC IOUT OUTPUT IIN INPUT VIN CURRENT SENSE VSENSE GND IGND ISENSE VOUT Table 4. Thermal Data Symbol Rthj-case Rthj-amb Parameter Thermal Resistance Junction-case Thermal Resistance Junction-ambient Max Max Value 1.3 51.3 (1) 37 (2) Unit C/W C/W Note: (1) When mounted on a standard single-sided FR-4 board with 0.5cm 2 of Cu (at least 35m thick). Note: (2) When mounted on a standard single-sided FR-4 board with 6 cm 2 of Cu (at least 35m thick). 3/19 VN920DSP ELECTRICAL CHARACTERISTICS (8V Tj=25C On State; VCC=13V; VIN=5V; IOUT=0A VIN=VOUT=0V VIN=0V; VOUT =3.5V VIN=VOUT=0V; VCC=13V; Tj =125C VIN=VOUT=0V; VCC=13V; Tj =25C IL(off1) IL(off2) IL(off3) IL(off4) Off Off Off Off State State State State Output Current Output Current Output Current Output Current Table 6. Switching (V CC=13V) Symbol td(on) td(off) dVOUT/ dt(on) dVOUT/ dt(off) Parameter Turn-on Delay Time Turn-off Delay Time Turn-on Voltage Slope Test Conditions RL=1.3 RL=1.3 RL=1.3 Min Typ 50 50 See relative diagram See relative diagram Max Unit s s V/s Turn-off Voltage Slope RL=1.3 V/s Table 7. Input Pin Symbol VIL IIL VIH IIH VI(hyst) VICL Parameter Input Low Level Low Level Input Current Input High Level High Level Input Current Input Hysteresis Voltage Input Clamp Voltage Test Conditions VIN=1.25V VIN=3.25V IIN=1mA IIN=-1mA 0.5 6 6.8 -0.7 Min 1 3.25 10 8 Typ Max 1.25 Unit V A V A V V V 4/19 VN920DSP ELECTRICAL CHARACTERISTICS (continued) Table 8. VCC - Output Diode Symbol VF Parameter Forward on Voltage Test Conditions -IOUT=5A; Tj=150C Min Typ Max 0.6 Unit V Table 9. Status Pin Symbol VSTAT ILSTAT CSTAT VSCL Parameter Test Conditions Status Low Output Voltage ISTAT =1.6mA Status Leakage Current Normal Operation VSTAT=5V Status Pin Input Normal Operation VSTAT=5V Capacitance ISTAT =1mA Status Clamp Voltage ISTAT =-1mA Min Typ Max 0.5 10 100 6 6.8 -0.7 8 Unit V A pF V V Table 10. Protections (see note 1) Symbol TTSD TR Thyst tSDL Ilim Vdemag Parameter Shut-down Temperature Reset Temperature Thermal Hysteresis Status delay in overload condition Current limitation Turn-off Output Clamp Voltage Test Conditions Min 150 135 7 Typ 175 15 20 30 5.5V Note: 1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device operates under abnormal conditions this software must limit the duration and number of activation cycles. Table 11. Openload Detection Symbol IOL tDOL(on) Parameter Openload ON State Detection Threshold Openload ON State Detection Delay Openload OFF State Voltage Detection Threshold Openload Detection Delay at Turn Off Test Conditions VIN=5V IOUT =0A Min 300 Typ 500 Max 700 200 Unit mA s VOL VIN=0V 1.5 2.5 3.5 V s tDOL(off) 1000 5/19 VN920DSP Figure 5. OPEN LOAD STATUS TIMING (with external pull-up) VOUT > VOL VIN IOUT< IOL OVERTEMP STATUS TIMING Tj > TTSD VIN VSTAT VSTAT tDOL(off) tDOL(on) tSDL tSDL Figure 6. Switching time Waveforms VOUT 90% 80% dVOUT/dt(on) dVOUT/dt(off) 10% t VIN td(on) td(off) t 6/19 VN920DSP Table 12. Truth Table CONDITIONS Normal Operation Current Limitation Overtemperature Undervoltage Overvoltage Output Voltage > VOL Output Current < IOL INPUT L H L H H L H L H L H L H L H OUTPUT L H L X X L L L L L L H H L H STATUS H H H (Tj < TTSD) H (Tj > TTSD) L H L X X H H L H H L Table 13. Electrical Transient Requirements On V CC Pin ISO T/R 7637/1 Test Pulse 1 2 3a 3b 4 5 ISO T/R 7637/1 Test Pulse 1 2 3a 3b 4 5 CLASS C E I -25 V +25 V -25 V +25 V -4 V +26.5 V II -50 V +50 V -50 V +50 V -5 V +46.5 V TEST LEVELS III -75 V +75 V -100 V +75 V -6 V +66.5 V TEST LEVELS RESULTS II III C C C C C C C C C C E E IV -100 V +100 V -150 V +100 V -7 V +86.5 V Delays and Impedance 2 ms 10 0.2 ms 10 0.1 s 50 0.1 s 50 100 ms, 0.01 400 ms, 2 I C C C C C C IV C C C C C E CONTENTS All functions of the device are performed as designed after exposure to disturbance. One or more functions of the device is not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device. 7/19 VN920DSP Figure 7. Waveforms NORMAL OPERATION INPUT LOAD VOLTAGE STATUS UNDERVOLTAGE VCC VUSD INPUT LOAD VOLTAGE STATUS undefined VUSDhyst OVERVOLTAGE VCC OPEN LOAD without external pull-up INPUT LOAD VOLTAGE STATUS Tj INPUT LOAD CURRENT STATUS TTSD TR OVERTEMPERATURE 8/19 VN920DSP Figure 8. Application Schematic +5V +5V Rprot STATUS VCC Dld C Rprot INPUT OUTPUT GND RGND VGND DGND GND PROTECTION REVERSE BATTERY NETWORK AGAINST Solution 1: Resistor in the ground line (RGND only). This can be used with any type of load. The following is an indication on how to dimension the RGND resistor. 1) RGND 600mV / (IS(on)max). 2) RGND (-VCC) / (-IGND) where -IGND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device's datasheet. Power Dissipation in RGND (when VCC<0: during reverse battery situations) is: PD= (-VCC)2/RGND This resistor can be shared amongst several different HSD. Please note that the value of this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the maximum on-state currents of the different devices. Please note that if the microprocessor ground is not common with the device ground then the RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output values. This shift will vary depending on many devices are ON in the case of several high side drivers sharing the same RGND. If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then the ST suggests to utilize Solution 2 (see below). Solution 2: A diode (DGND) in the ground line. A resistor (RGND=1k) should be inserted in parallel to DGND if the device will be driving an inductive load. This small signal diode can be safely shared amongst several different HSD. Also in this case, the presence of the ground network will produce a shift (j600mV) in the input threshold and the status output values if the microprocessor ground is not common with the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network. Series resistor in INPUT line is also required to prevent that, during battery voltage transient, the current exceeds the Absolute Maximum Rating. Safest configuration for unused INPUT pin is to leave it unconnected, while unused SENSE pin has to be connected to Ground pin. LOAD DUMP PROTECTION Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds VCC max DC rating. The same applies if the device will be subject to transients on the VCC line that are greater than the ones shown in the ISO T/R 7637/1 table. C I/Os PROTECTION: If a ground protection network is used and negative transient are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to prevent the C I/Os pins to latch-up. The value of these resistors is a compromise between the leakage current of C and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of C I/Os. -VCCpeak/Ilatchup Rprot (VOHC-VIH-VGND) / IIHmax Calculation example: For VCCpeak= - 100V and Ilatchup 20mA; VOHC 4.5V 5k Rprot 65k. Recommended Rprot value is 10k. 9/19 VN920DSP Figure 9. Off State Output Current IL(off1) (uA) 9 8 7 6 5 2.5 4 2 3 2 1 0 -50 -25 0 25 50 75 100 125 150 175 1.5 1 0.5 0 -50 -25 0 25 50 75 100 125 150 175 Figure 10. High Level Input Current Iih (uA) 5 4.5 Vin=3.25V 4 3.5 3 Tc (C) Tc (C) Figure 11. Input Low Level Vil (V) 2.6 2.4 2.2 2 1.8 1.6 1.4 1.2 1 -50 -25 0 25 50 75 100 125 150 175 Figure 13. Input High Level Vih (V) 3.6 3.4 3.2 3 2.8 2.6 2.4 2.2 2 -50 -25 0 25 50 75 100 125 150 175 Tc (C) Tc (C) Figure 12. Input Clamp Voltage Vicl (V) 8 7.8 Figure 14. Input Hysteresis Voltage Vhyst (V) 1.5 1.4 Iin=1mA 7.6 7.4 7.2 7 6.8 6.6 6.4 6.2 6 -50 -25 0 25 50 75 100 125 150 175 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 -50 -25 0 25 50 75 100 125 150 175 Tc (C) Tc (C) 10/19 VN920DSP Figure 15. Overvoltage Shutdown Vov (V) 50 48 46 44 42 40 38 36 34 32 30 -50 -25 0 25 50 75 100 125 150 175 Figure 18. ILIM Vs Tcase Ilim (A) 100 90 Vcc=13V 80 70 60 50 40 30 20 10 0 -50 -25 0 25 50 75 100 125 150 175 Tc (C) Tc (C) Figure 16. Turn-on Voltage Slope dVout/dt(on) (V/ms) 700 650 600 550 500 450 400 350 Figure 19. Turn-off Voltage Slope dVout/dt(off) (V/ms) 550 500 Vcc=13V Rl=1.3Ohm 450 400 350 300 250 200 150 100 Vcc=13V Rl=1.3Ohm 300 250 -50 -25 0 25 50 75 100 125 150 175 50 0 -50 -25 0 25 50 75 100 125 150 175 Tc (C) Tc (C) Figure 17. On State Resistance Vs Tcase Ron (mOhm) 50 45 40 35 30 25 20 15 10 5 0 -50 -25 0 25 50 75 100 125 150 175 Figure 20. On State Resistance Vs VCC Ron (mOhm) 50 45 Iout=10A Vcc=8V; 36V 40 35 Tc= 150C 30 25 20 Tc= 25C 15 10 Tc= - 40C 5 0 5 10 15 20 25 30 35 40 Tc (C) Vcc (V) 11/19 VN920DSP Figure 21. Status Leakage Current Ilstat(A) 0.05 0.045 Figure 23. Status Low Output Voltage Vstat (V) 0.8 0.7 Vstat=5V 0.04 0.035 0.03 0.025 0.02 0.015 Istat=1.6mA 0.6 0.5 0.4 0.3 0.2 0.01 0.005 0 -50 -25 0 25 50 75 100 125 150 175 0.1 0 -50 -25 0 25 50 75 100 125 150 175 Tc (C) Tc (C) Figure 22. Status Clamp Voltage Vscl (V) 8 7.8 Istat=1mA 7.6 7.4 7.2 7 6.8 6.6 6.4 6.2 6 -50 -25 0 25 50 75 100 125 150 175 Tc (C) 12/19 VN920DSP Figure 24. Maximum turn off current versus load inductance ILMAX (A) 100 A B 10 C 1 0.1 1 L(m H ) A = Single Pulse at TJstart=150C B= Repetitive pulse at T Jstart=100C C= Repetitive Pulse at T Jstart=125C Conditions: VCC=13.5V Values are generated with R L=0 In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves B and C. 10 100 VIN, IL Demagnetization Demagnetization Demagnetization t 13/19 VN920DSP PowerSO-10TM Thermal Data Figure 25. PowerSO-10TM PC Board Layout condition of Rth and Zth measurements (PCB FR4 area= 58mm x 58mm, PCB thickness=2mm, Cu thickness=35m, Copper areas: from minimum pad lay-out to 8cm2). Figure 26. Rthj-amb Vs PCB copper area in open box free air condition RTHj_amb (C/W) 55 Tj-Tamb=50C 50 45 40 35 30 0 2 4 6 8 10 PCB Cu heatsink area (cm^2) 14/19 VN920DSP Figure 27. PowerSO-10 Thermal Impedance Junction Ambient Single Pulse ZTH (C/W) 100 Footprint 6 cm 2 10 1 0.1 0.01 0.0001 0.001 0.01 0.1 1 10 100 1000 Time (s) Figure 28. Thermal fitting model of a double channel HSD in PowerSO-10 Pulse calculation formula Z TH = R TH + Z THtp ( 1 - ) where = tp T Table 14. Thermal Parameter Area/island (cm2) R1 (C/W) R2 (C/W) R3( C/W) R4 (C/W) R5 (C/W) R6 (C/W) C1 (W.s/C) C2 (W.s/C) C3 (W.s/C) C4 (W.s/C) C5 (W.s/C) C6 (W.s/C) Footprint 0.02 0.1 0.2 0.8 12 37 0.0015 7.00E-03 0.015 0.3 0.75 3 6 Tj C1 C2 C3 C4 C5 C6 R1 R2 R3 R4 R5 R6 Pd T_amb 22 5 15/19 VN920DSP PACKAGE MECHANICAL Table 15. PowerSO-10TM Mechanical Data Symbol A A (*) A1 B B (*) C C (*) D D1 E E2 E2 (*) E4 E4 (*) e F F (*) H H (*) h L L (*) a (*) Note: (*) Muar only POA P013P millimeters Min 3.35 3.4 0.00 0.40 0.37 0.35 0.23 9.40 7.40 9.30 7.20 7.30 5.90 5.90 1.27 1.25 1.20 13.80 13.85 0.50 1.20 0.80 0 2 1.80 1.10 8 8 1.35 1.40 14.40 14.35 Typ Max 3.65 3.6 0.10 0.60 0.53 0.55 0.32 9.60 7.60 9.50 7.60 7.50 6.10 6.30 Figure 29. PowerSO-10TM Package Dimensions B 0.10 A B 10 H E E2 E4 1 SEATING PLANE e 0.25 B DETAIL "A" A C D = D1 = = = SEATING PLANE h A F A1 A1 L DETAIL "A" P095A 16/19 VN920DSP Figure 30. PowerSO-10TM Suggested Pad Layout And Tube Shipment (no suffix) 14.6 - 14.9 10.8 - 11 6.30 A A C C CASABLANCA B MUAR 0.67 - 0.73 1 2 3 4 5 10 9 8 7 6 0.54 - 0.6 B 9.5 All dimensions are in mm. 1.27 Base Q.ty Bulk Q.ty Tube length ( 0.5) Casablanca Muar 50 50 1000 1000 532 532 A B C ( 0.1) 0.8 0.8 10.4 16.4 4.9 17.2 Figure 31. Tape And Reel Shipment (suffix "13TR") REEL DIMENSIONS Base Q.ty Bulk Q.ty A (max) B (min) C ( 0.2) F G (+ 2 / -0) N (min) T (max) 600 600 330 1.5 13 20.2 24.4 60 30.4 All dimensions are in mm. TAPE DIMENSIONS According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing W P0 ( 0.1) P D ( 0.1/-0) D1 (min) F ( 0.05) K (max) P1 ( 0.1) 24 4 24 1.5 1.5 11.5 6.5 2 End All dimensions are in mm. Start Top cover tape 500mm min Empty components pockets saled with cover tape. User direction of feed 500mm min No components Components No components 17/19 VN920DSP REVISION HISTORY Date Sep. 2004 Oct. 2004 Revision 1 - First Issue. 2 - Minor text change. Description of Changes 18/19 VN920DSP Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 19/19 |
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